Automated Evaluation of Student Designs in Digital System Design Laboratories

Rigorous evaluation of the functionality and originality of student designs in upper level digital system design courses is challenging at best. Courses such as the ASIC (Application Specific Integrated Circuit) Design Laboratory and Computer Design and Prototyping Laboratory require students to create simulations and hardware realizations of systems that have complex functional and performance requirements. Student demonstrations are usually inadequate to verify much more than a minimal subset of required functionality. Furthermore, it can be time consuming to verify in a simulation or FPGA prototype based demonstration that the design being demonstrated is in fact the student’s design. In the ASIC design Laboratory and the Computer design and prototyping Laboratory, several automated processes have been developed to verify the correct functionality and originality of student designs. In this paper, examples are presented of design requirements to be verified, the means developed to evaluate the designs, and results of these evaluations.